The present invention is directed to integrated circuit semiconductor devices incorporating junctions of varying conductivity types designed to conduct current and methods of making such devices. More specifically, the present invention relates to a capacitor structure for integrated circuit semiconductor devices employing a dual damascene interconnect system and a process for fabricating such capacitors.
In integrated circuit semiconductor devices, capacitors can be formed as junction capacitors or thin-film capacitors. As is known, the application of a reverse bias voltage across a semiconductor junction forces the mobile carriers to move away from the junction thereby creating a depletion region. The depletion region acts as the dielectric of a parallel-plate capacitor, with the depletion width representing the distance between the plates. Thus the junction capacitance is a function of the depletion width, which is in turn a function of the applied reverse bias and the impurity concentrations in the vicinity of the junction.
Thin-film capacitors, which are a direct miniaturization of conventional discrete parallel-plate capacitors, can be also be fabricated in an integrated circuit. Like the discrete capacitor, the thin-film capacitor comprises two conductive layers separated by a dielectric. One type of thin-film capacitor is formed as a metal-oxide-semiconductor capacitor, having a highly doped bottom plate, a silicon dioxide dielectric layer, and a metal top plate. The dielectric layer can also be formed from other materials, such as tantalum pentoxide, barium titanate, strontium titanate and barium strontium titanate, silicon nitride or silicon dioxide. The bottom plate is typically formed from highly doped polycrystalline silicon (polysilicon). The top plate can be formed from various metals, including titanium nitride, titanium, tungsten or platinum. Alternatively, a thin-film capacitor can be formed with two metal layers forming the top and bottom plates, separated by the dielectric layer. The layers are patterned and etched to achieve the desired size and capacitance value.
Conventionally, the interconnection between device active areas formed in a semiconductor substrate is provided by conductive metal layers including conductive traces or lines formed in multiple levels of the substrate and interconnected by conductive vertical vias or plugs. First level vias provide electrical connection to the device active areas. Vias at higher levels interconnect adjacent levels of conductive traces. Forming these metallization layers requires conductor deposition, patterning, masking and etching steps to form the conductive traces, and patterning and deposition steps to form the conductive plugs.
Metal vias connected to device active areas (e.g., the electrode of a MOSFET gate, or the source and drain regions) are typically referred to as the metal-1 metallization layer or the first level of metallization. Metal vias in upper levels interconnect vertically-adjacent conductive traces, where the conductive traces are referred to as the metal-2 layer. For simplicity, both metal-to-semiconductor and metal-to-metal electrical connections are referred to herein as metal interconnections or metal interconnects.
Recently, great interest has been shown in the use of copper alloys for metalization within semiconductor devices. Compared with aluminum, copper has both beneficial electromigration resistance and a relatively low resistivity of about 1.7 micro-ohm-cm. Unfortunately, copper is a difficult material to etch. Consequently, dual damascene processes have been developed to simplify the process and eliminate metal etching steps.
The dual damascene structure has a lower conductive via that contacts an underlying device active area or an underlying conductive runner in a lower interconnect level. Thus the conductive via provides the same function as the plug structure in a traditional interconnect system. The dual damascene structure further includes an upper inlaid conductive runner to interconnect conductive vias. The conductive vias and the interconnecting conductive runners are formed by first forming vias and interconnecting horizontal trenches within a dielectric layer of the device. Then a conductive material, e.g., copper, is simultaneously deposited in both the vias and trenches. This process eliminates the need to form a plug structure and an overlying conductive layer during separate processing steps, according to the conventional interconnect system.
Capacitors can be formed within a well formed within a dual damascene structure as described in the commonly-assigned U.S. Pat. No. 6,320,244. The capacitor comprises three overlying layers formed within the well, including a first electrode lining the well, a capacitor dielectric layer formed thereover, and a second electrode formed over the dielectric layer.
A capacitor for a dual damascene interconnection system comprises a bottom plate, a capacitor dielectric layer and a top plate formed in a dielectric substrate. The dielectric substrate overlies a barrier layer on the upper surface of a dual damascene structure, including conductive vias and overlying conductive runners. Each of the conductive vias is electrically connected to one of the top or bottom plate of the capacitor.